文章基本信息

标题：Design and Implementation of Address cum Data bus Encoder for Low Power
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作者：Shankaranarayana Bhat M ; Vivek Hegde N ; Cletus Crasta 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2017
卷号：6
期号：11
页码：1646-1649
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Power dissipation is a major concern in today’s VLSI circuits and systems as it adversely impacts feasibility, portability, and reliability. The power dissipation in buses is significant in such systems and constitutes a substantial portion of the dynamic power consumed. Bus encoding techniques were developed for reducing bus power by way of encoding the data before they were sent on the buses. The encoding techniques will be of either redundant or irredundant type based on whether they employ extra bus lines for their operation or not. The paper focuses on design and implementation of an irredundant encoding technique called AMBITS, which is an adapted version of MBITS suitable for multiplexed data and address buses. The number of bit transitions and power dissipation in the case of AMBITS was found to be less than that of MBITS. However, the power and the area overhead for the encoder and decoder in the case of AMBITS were found slightly higher compared to the MBITS on the implementation of physical design using Cadence tool.
关键词：Bus encoding; Low power VLSI; Switching activity; Power dissipation.