文章基本信息

标题：A system-on-chip 1.5 GHz phase locked loop realized using 40 nm CMOS technology
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作者：Wang, Weiyin ; Chen, Xiangjie ; Wong, Hei 等
期刊名称：Facta universitatis - series: Electronics and Energetics
印刷版ISSN：0353-3670
电子版ISSN：2217-5997
出版年度：2018
卷号：31
期号：1
页码：101-113
DOI：10.2298/FUEE1801101W
出版社：University of Niš
摘要：This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.
关键词：PLL; blind zone; current mismatch; ring oscillator