文章基本信息

标题：A 0.88nS Settling Time 115V Settling Error with 68.18dB SNDR Continuous-time Common-Mode Feedback (CMFB) Circuit in 180nm CMOS Technology
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作者：Sina Mahdavi ; Faeze Noruzpur ; Leyla Alizadeh 等
期刊名称：International Journal of Mechatronics, Electrical and Computer Technology
印刷版ISSN：2305-0543
出版年度：2017
卷号：7
期号：26
页码：3674-3684
出版社：Austrian E-Journals of Universal Scientific Organization
摘要：This paper proposes a new high-speed and high-linear continuous-time Common-Mode Feedback Block (CMFB) circuit. The main purposes of the proposed idea are to increase the speed and linearity of the CMFB, reliably. Utilizing the worst case simulation on the proposed CMFB circuit, the output voltage can be settled in the preferred level just after 0.88nS. As simulation results prove that, at 1.8 V supply voltage and 100 MS/s sampling rate with a Nyquist input (49.9MHz), the amplifier achieves a SNDR of 68.18dB and a consistent ENOB of 11.07bit consistently. The power consumption of the suggested CMFB is 374μW with the power supply of 1.8 volts, also the settling time error is 115μV. Moreover, as simulation result demonstrates, exerting the reference voltage (Vref) from 0.6 to 1.35 volts the suggested circuit be able to adjust the output value in the suitable level with low error properly. Also, DC gain of the amplifier is 67dB, and the phase margin is 60 and 72.5 degree without and with considering the capacitor load at the output of the amplifier respectively, meanwhile, for this case the unity gain bandwidth is 1.5GHz and 886MHz correspondingly. It is notable that, 1pF capacitor load is applied to the output nodes of the amplifier. The chip area of the proposed CMFB is 16.2μm*22μm, also for operation correctness of the CMFB, Monte-Carlo simulations are applied to the amplifier too, evidently. Simulation results are done using the HSPICE BSIM3 model of a 0.18μm CMOS technology.
关键词：Amplifier; Common-mode feedback; Power consumption; Telescopic; High-speed