期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN:2347-6710
电子版ISSN:2319-8753
出版年度:2018
卷号:7
期号:4
页码:3385
DOI:10.15680/IJIRSET.2018.0704022
出版社:S&S Publications
摘要:Golay Code is a type of Error Correction code discovered and performance very close to Shanon‟s limit. Good error correcting performance enables reliable communication. Since its discovery by Marcel J.E. Golay there ismore research going on for its efficient construction and implementation. The binary Golay code (G23) is representedas (23, 12, 7), while the extended binary Golay code (G24) is as (24, 12, 8). High speed with low-latency architecturehas been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shiftregister. This brief also presents an optimized and low-complexity decoding architecture for extended binary Golaycode (24, 12, 8) based on an incomplete maximum likelihood decoding scheme.
关键词:Golay Code; Decoder; Encoder; Field Programmable Gate Array (FPGA)