文章基本信息

标题：Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology
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作者：T. Suguna ; M. Janaki Rani
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2018
卷号：9
期号：1
页码：1
DOI：10.5121/vlsic.2018.9101
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：CMOS technology is the key element in the development of VLSI systems since it consumes less power.Power optimization has become an overridden concern in deep submicron CMOS technologies. Due toshrink in the size of device, reduction in power consumption and over all power management on the chipare the key challenges. For many designs power optimization is important in order to reduce package costand to extend battery life. In power optimization leakage also plays a very important role because it hassignificant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate thedevelopments and advancements in the area of power optimization of CMOS circuits in deep submicronregion. This survey will be useful for the designer for selecting a suitable technique depending upon therequirement.
关键词：leakage power; low power; voltage scaling; power gating; transistor stacking; adiabatic logic.