文章基本信息

标题：Leakage Reduction Technique and Analysis of CMOS D Flip Flop
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作者：Sridhara K ; G S Biradar
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2016
卷号：7
期号：4
页码：39
DOI：10.5121/vlsic.2016.7404
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Power consumption and delay are the two major issues in the design of today‘s VLSI based batteryoperated portable electronic devices. Memory units in these devices are made of flip flops and each flipflop will consume more power in both active and idle conditions. Through this paper we try to explorealternate techniques to implement D flip-flop with the aim of reducing leakage power, delay and toincrease the speed. All the different configurations of D flip-flops are simulated using HSPICE in 90nmprocess technology with BSIM4 MOS transistor models of level 54.
关键词：Pass transistor; Transistor stacking; Leakage Power; LECTOR; VCLEARIT