期刊名称:Journal of Theoretical and Applied Information Technology
印刷版ISSN:1992-8645
电子版ISSN:1817-3195
出版年度:2015
卷号:79
期号:1
出版社:Journal of Theoretical and Applied
摘要:The Bose, Chaudhuri, and Hocquenghem (BCH) codes are being widely used in variety communication and storage systems. In this paper, a simplified algorithm for BCH decoding is proposed in order to reduce the implementation complexity. Error locator polynomial with Peterson algorithm is proposed for both a quick result and very low components instead of the Berlekamp�s algorithm that uses the iterative method. In addition, a modified Chien search block is proposed to reduce the hardware complexity. This algorithm reduces the number of logic gates. Consequently, it reduces the power consumption with a percentage which can achieve 32 % compared to the basic algorithm. We developed the design of the proposed algorithm, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of BCH decoder on FPGA card.
关键词:FPGA implementation; BCH decoder; add syndromes; iterations; Digital Video Broadcasting-Satellite-Second Generation