文章基本信息

标题：INCORPORATION OF REDUCED 09, 0B, 0D AND 0E STRUCTURES INTO INVERSE MIX COLUMNS FOR AES-128 TECHNIQUE
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作者：M.SENTHIL KUMAR ; Dr.S.RAJALAKSHMI
期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：70
期号：1
出版社：Journal of Theoretical and Applied
摘要：Cryptography technique plays a vital role in Signal Processing, Wireless Communication, Satellite Communication, Cellular Mobile Communication and Wi-Max for high security features. AES Encryption is performed to convert plain text into cipher text, and AES Decryption is used to retrieve the original information through some secure Key. Encryption process is divided into Sub-Bytes, Shift-Rows, Mix-Column and Add Round key. Decryption process is split into Inverse Sub-Bytes, Inverse Shift-Rows, Add Round Key and Inverse Mix-Columns. Conventional AES Mix-Columns and Inverse Mix-columns are designed using X-Time unit. X-time unit is used to perform shift and XOR operation more than one time. Hence it consumes more area, delay and power. To overcome this problem, Inverse Mix-Columns unit is designed using reduced 09, 0B, 0D and 0E structures which perform 3 shift operations directly than XOR with fixed coefficient 1B. Number of Shift and XOR operation is reduced in proposed Inverse Mix-Columns structure. Hence reduced Inverse Mix-Columns based AES decryption provides less area, delay and power than conventional X-Time based AES decryption process. Simulation is performed by ModelSim6.3c and Synthesis is carried out Xilinx10.1. Implementation is performed on FPGA Spartan3 device.
关键词：Cryptography; X-Time unit; Reduced Inverse Mix-Columns; Modified 09; 0B; 0D and 0E structures FPGA.