文章基本信息

标题：DESIGN AND ANALYSIS OF LOW POWER HYBRID ADDER
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作者：M.JAYAPRAKASH ; Dr.A.SHANMUGAM ; M.Peer Mohamed 等
期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：58
期号：3
出版社：Journal of Theoretical and Applied
摘要：For any digital system, digital signal processing or control system addition is a core operation. The performance of the resident adders greatly influences rapid and accurate operation of digital systems. Adders are one of the most prominent components in digital systems, as they are broadly used in other basic digital operations such as subtraction, multiplication and division. Improved the performance of the adder would therefore greatly advance the execution of operation greatly advance the execution of operations inside a circuit compromised of such blocks [1]. A comparative analysis on power consumption in three different adders, each offering different advantages and having tradeoffs has been performed based on circuit complexity and power consumption. The pioneer of CMOS traditional adder circuits, which consumes more power when compared to other two adders. The total number of transistors required for conventional CMOS adder is 28. Recently, it has been proved that the multiplexer-based multiplier outperforms the modified Booth multiplier both in speed and power dissipation by 13% to 26%, due to small internal capacitance [2]. The performance characteristics of conventional multiplier types which observed, it is found that the multiplexer-based and Transmission Gate based multiplication algorithm is more advantageous, especially when the size of the multiplied numbers is small. The number of transistors required for multiplexer based adders is 16. A heuristic approach, known as hybrid adder models is proposed to achieve optimal power savings at smaller geometry sizes. This hybrid adder model that consumes low power among three adders and the transistors required are 12. The design is simulated using MOSIS 90nm technology.
关键词：Full Adder; Hybrid Adder; CMOS; Multiplexer; MOSIS