文章基本信息

标题：RECONFIGURABLE FIR FILTER WITH RADIX-4 ARRAY MULTIPLIER
本地全文：下载
作者：S.KARTHICK ; Dr. S. VALARMATHY ; E.PRABHU 等
期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：57
期号：3
出版社：Journal of Theoretical and Applied
摘要：FIR filters are commonly used digital filters which find its major application in digital signal processing. In conventional FIR filter, the input vector form is delayed by one sample and then multiplied with filter coefficients which are subsequently accumulated by the adders. The drawbacks due to this are high device utilization and high power consumption. In order to compensate these drawbacks, we propose a reconfigurable FIR filter using radix-4 multiplier. The major changes in the proposed system are radix-4 multiplier for multiplication and change in the basic architecture of the FIR filter. In this method, we combine all the input tap values having similar co-efficient values and then multiplying those with the respective co-efficient. The proposed design is simulated and synthesized using Xilinx. The proposed method is compared with the existing FIR filter. From the results, it is observed that our proposed method has got better results by having less number of occupied slices and low power consumption. The power analysis report of a 8-tap FIR filter using the proposed approach consumes 60�W at 25MHz, 110�W at 50MHz, 170�W at 75MHz and 220�W at 100MHz compared with the existing approach which was implemented on Spartan-3E. Additionally, the proposed design was also tested for n-tap FIR filter implemented in Virtex-4 FPGA and compared with the existing technique, which shows that our approach minimizes the number of slices occupied by the design and reduces the power consumption.
关键词：Reconfigurable FIR Filter; Radix 4 Multiplier; Power Consumption; Device Utilization.