文章基本信息

标题：HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS
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作者：M. Thiyagarajan ; R. Manikandan
期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2011
卷号：26
期号：2
出版社：Journal of Theoretical and Applied
摘要：VLSI Cell partitioning is considered as Hypergraph model, which can be a treated a randomized algorithm through the markov chain. This approach helps to give a probabilistic algorithm through transition probability matrices of a markov chain for VLSI partitioning. In the second model SAT problem situation is used to model FPGA Layout. As almost all problems posed in VLSI design and analysis are NP-Complete, any attempt to solve them is to identify some reduction tool to NP-Complete problems. One such reduction is attempted through SAT Problem.
关键词：Hyper Graph; Markov Chain ;Max-Min Cut; Adjacency Matrix; SAT Problem; FPGA Layout; NP-Complete Reduction; Formal Language ; Time Complexity