期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2007
卷号：7
期号：10
页码：202-219
出版社：International Journal of Computer Science and Network Security
摘要：This paper examines the extension of constructive library-aware logic synthesis to the physical placement stage of integrated circuit design. Constructive logic synthesis differs from traditional synthesis approaches in that it builds a circuit netlist incrementally starting from the primary inputs and proceeding towards the primary outputs. In each iteration of this procedure, the semantic structure of the unsynthesized logic functions is utilized to identify and extract a small subcircuit that consists of library primitives reflecting that structure. The algorithm interleaves the steps of technology-independent decomposition and technology-dependent mapping into library cells in a way that mitigates its greedy nature. Conjecturing that adding a placement step to this methodology would further improve synthesis quality we developed a system which synthesizes circuits by incremental decomposition, mapping, and placement. We describe the algorithms used in this system and analyze the quality of the designs it generates under a variety of options for decomposition and placement. The empirical results we obtained, however, suggest that adding a placement step to constructive synthesis produces no noticeable improvement in design quality. This strongly suggests that our original conjecture is false, and we examine possible reasons for such a negative result.
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