期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2008
卷号：8
期号：11
页码：226-237
出版社：International Journal of Computer Science and Network Security
摘要：Design reuse and verification reuse are important to satisfy time-to-market requirements. Designer must be able to reuse Intellectual Property in the design as golden model. Reuse of verification environment across different designs of the domain saves time to market further and improves total design verification quality. The Physical Layer is a fundamental layer upon which all higher level functions in a network are based. However, due to the plethora of available hardware technologies with widely varying characteristics, this is perhaps the most complex layer in the OSI architecture. The implementation of this layer is often termed Physical layer device (PHY). The Physical Layer defines the means of transmitting raw bits rather than logical data packets over a physical link connecting network nodes. A PHY chip is commonly found on Ethernet devices. Its purpose is digital access of the modulated link and interface to Ethernet Media Access Control (MAC) using media independent interface (MII) interface. This paper discusses Verification process, issues involved in verification process and Test Methodologies. A broad outline of the comparison of traditional verilog and specman verification methodologies has been presented here. It also explains verification strategy and reuse of design environment with reference to verifying the Ethernet packet in Ethernet Intellectual Property (IP) Core. Design Reuse is achieved through verilog tasks which were used in specman environment. Ethernet Phy e Verification component (eVC) is an in house development. Ethernet eVC is built with phy as a separate eVC and host being a task driven verilog Bus functional model (BFM). This allowed us to create a virtual host environment using a combination of verilog BFM and eVC. Verification environment reuse for different application with different interface is done by developing a wrapper around the Design Under Test (DUT) interface and then interfacing it to the environment. A detailed test plan is made for the complete and exhaustive test for Ethernet MAC Receiver. Coverage goals, coverage obtained and coverage analysis indicate efficiency of the verification methodology.
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