文章基本信息

标题：Bounded Depth Circuits with Weighted Symmetric Gates: Satisfiability, Lower Bounds and Compression
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作者：Takayuki Sakai ; Kazuhisa Seto ; Suguru Tamaki 等
期刊名称：LIPIcs : Leibniz International Proceedings in Informatics
电子版ISSN：1868-8969
出版年度：2016
卷号：58
页码：82:1-82:16
DOI：10.4230/LIPIcs.MFCS.2016.82
出版社：Schloss Dagstuhl -- Leibniz-Zentrum fuer Informatik
摘要：A Boolean function f:{0,1}^n -> {0,1} is weighted symmetric if there exist a function g: Z -> {0,1} and integers w_0, w_1, ..., w_n such that f(x_1, ...,x_n) = g(w_0+sum_{i=1}^n w_i x_i) holds. In this paper, we present algorithms for the circuit satisfiability problem of bounded depth circuits with AND, OR, NOT gates and a limited number of weighted symmetric gates. Our algorithms run in time super-polynomially faster than 2^n even when the number of gates is super-polynomial and the maximum weight of symmetric gates is nearly exponential. With an additional trick, we give an algorithm for the maximum satisfiability problem that runs in time poly(n^t)*2^{n-n^{1/O(t)}} for instances with n variables, O(n^t) clauses and arbitrary weights. To the best of our knowledge, this is the first moderately exponential time algorithm even for Max 2SAT instances with arbitrary weights. Through the analysis of our algorithms, we obtain average-case lower bounds and compression algorithms for such circuits and worst-case lower bounds for majority votes of such circuits, where all the lower bounds are against the generalized Andreev function. Our average-case lower bounds might be of independent interest in the sense that previous ones for similar circuits with arbitrary symmetric gates rely on communication complexity lower bounds while ours are based on the restriction method.
关键词：exponential time algorithm; circuit complexity; circuit minimization; maximum satisfiability