文章基本信息

标题：Implementation of Arithmetic Logic Unit Using FINFET
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作者：Neeraj Jatav ; Ayushi Marwah ; Shyam Akashe 等
期刊名称：International Journal of Hybrid Information Technology
印刷版ISSN：1738-9968
出版年度：2016
卷号：9
期号：9
页码：335-342
出版社：SERSC
摘要：Today to complete the extra and difficult task the demand of refining ability of a processor is increasing step by step which resulted in the more fabrication of components fabricated on a single chip as the Moore Law. But with accumulative in a modulethenoise rises. The ALU is a one of the most important functional unitsin any CPU. The ALU is a core of any system or any processor as well as the core module of the central processing unit CPU. Since mostly all the simple operations are executed by the support of ALU only. As the name ALU denotes arithmetic logic unit, therefore it is used to execute the arithmetic and logical task in a digital bit. So the ALU can be definedas the combination unit which is used to implement its logical and arithmetic function units. The determination of this paper is to implement the Arithmetic Logic Unit (ALU) by a FinFet technique in 45nm. The workaccomplishedby ALU isLogic Action (OR, AND and EXOR) and Arithmetic action (ADDER). This result is before certain to the multiplexer and the result obtained is dependent on the input selectorline. This result obtained is considered is in the term of average power and noise and paralleled with the dissimilar input value. The application takesdomicile in a tool cadence virtuoso.In this paper is to present a modified low power ALU using Fin type field-effect transistors (FinFETs) technique and to compare that with the GDI technique at 45nm
关键词：ALU (;Arithmetic;Logic Unit;); CADENCE;VIRTUOSO (;tool;); FINFET; GDI ;TECHNIQUE (;gate diffusion input;)