文章基本信息

标题：Design of Instruction Fetch Unit and ALU for Pipelined RISC Processor
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作者：Sarika U. Kadam ; Samadhan D. Mali
期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2016
卷号：5
期号：2
页码：15867-15869
DOI：10.18535/ijecs/v5i2.36
出版社：IJECS
摘要：Pipelining is a concept which improves the performance of processor. A five stage pipelined RISC processor has stages asinstruction fetch, decode, execute, memory, write back. RISC has a simpler and faster instruction set architecture. The aim of paper is todesign instruction fetch unit and ALU which are part of RISC processor architecture. Instruction fetch is designed to read theinstructions present in memory. ALU is in the execution stage of pipelining which performs all computations i.e. arithmetic and logicaloperations. Xilinx 8.1i is used to simulate the design using VHDL language
关键词：Instruction; Pipeline; RISC; VHDL