文章基本信息

标题：An FPGA Implementation of 1553 Protocol Controller
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作者：Jemti Jose
期刊名称：International Journal of Computer Information Systems and Industrial Management Applications
印刷版ISSN：2150-7988
电子版ISSN：2150-7988
出版年度：2014
期号：6
页码：66-76
出版社：Machine Intelligence Research Labs (MIR Labs)
摘要：In a modern military avionics system all the devices need to communicate as efficiently as possible with a minimum amount of hardware. 1553 is a dual- redundant, bi-directional, Manchester encoded, digital time division command/ response data bus which eliminates the use of point-to-point wiring. It uses a shielded twisted pair wire for data transfer. This bus can allow communication between any devices (maximum of 31) connected to it. Even though 1553 is an old standard (developed in early 1970s), it is an inevitable part of almost all aircrafts of today. Compared to other avionics data bus standards 1553 is known for its reliability and flexibility. With the presented method, the protocol controller is modeled as state machine in HDL. This paper describes implementation of the Military data bus standard MIL-STD-1553 onto a Xilinx based FPGA platform.
关键词：1553 data bus; Bus Controller (BC); Remote Terminal ; (RT); Command Word (CW); Data Word (DW); Status Word (SW); ; FPGA; HDL