文章基本信息

标题：Design and FPGA Implementation of Optimized Parallel Prefix Adder
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作者：Anjana D ; Jemti Jose
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：7
页码：12975
DOI：10.15680/IJIRSET.2016.0507161
出版社：S&S Publications
摘要：Binary addition is the frequently used arithmetic operation in most of the digital system. The accurateoperation of a digital system is greatly influenced by the performance of adders. Thus improving performance of thedigital adder would greatly advance the execution of binary operations. Speed of the adder decides the minimum clockcycle time in a microprocessor. The need for a Parallel Prefix adder is that it is primarily fast when compared withripple carry adders. Parallel prefix adders are the most efficient circuits for binary addition. Their structure and fastperformance makes them attractive for VLSI implementation. Parallel prefix adders (PPA) are family of adders whichare derived from the commonly known carry lookahead adders. These adders are mainly used for adders with widerword lengths.
关键词：Parallel prefix adders; Carry look ahead adders.