文章基本信息

标题：Clock-Gated Double-Edge Triggered Flip-Flop for Effectual Power Reduction
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作者：K.Raja ; Dr.S.Saravanan ; Sunanda saga 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：MULTICON
页码：513
出版社：S&S Publications
摘要：In recent years, mobile and portable information systems are pushing electronics and its developmentprocess. The only driving force behind the need for dramatic reduction of power dissipation in IC is to drive low-powerdesigns. For asynchronous designs, the power consumption is mainly due to the storage elements and the clockdistribution. Energy reduced from clock elements plays critical role in low-power designs. Clock gating is one of theefficient techniques to reduce the dynamic power. The use of double edge triggered flip flop instead of single edgetriggered flip flop may result in significant power reduction. However incorporating the clock-gating technique with theDETFF reduces dynamic power consumption but introduces an asynchronous data sampling. Two solutions areproposed to suppress this issue in DETFFs. Each solution has its own limitations. Thus in order to overcome thedrawback of the existing method, we hereby propose the DETFF method in which the positive flip-flop and negativeflip-flop are connected in parallel. It is designed using one transmission gate and two inverters and the output is fed tothe MUX as input. The output of MUX is then strengthened using the inverters. Thus the flip-flopped data is sent to theinverter to get absolute data at the output. This proposed method can reduce about (3-5) % of power consumption.
关键词：Clock-gating; low-power; asynchronous sampling; DETFF; MUX; inverters.