文章基本信息

标题：A Low Transition Test Pattern Generation of Multiple SIC Vectors Based on Bist Schemes
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作者：T.Jeeva ; G.Mohanraj ; A.Sathish Kumar 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：MULTICON
页码：422
出版社：S&S Publications
摘要：A novel TPG (Test Pattern Generator) is proposed for L-BIST (Logical-Built In Self Test) schemes.Unlike conventional TPGs, the proposed TPG generates the MSIC vectors (Multiple single input changes) whiletraditional systems like seed generator and conventional XOR-seed generator clocked by two non-overlapping clocksgenerates SIC vectors for test the entire CUT (circuit-under test ). Besides some of the schemes which are used fortesting in not flexible for both test-per clock as well as test per scan scheme but this scheme is not a constraint. The twosub-modules are combined together to achieve the minimum transitions sequence thus MSIC vectors namely“reconfigurable Johnson-counter and old seed-generator” (XOR base) the outputs of both systems are finally XOR withone another. So an n-bit seed generator and m-bit Johnson counter generates the Xmn output vectors for testing theCUT. Due to this vector, a large amount of test coverage is achieved then fault coverage. The entire testing scheme isdesigned as well as simulated using Quartus II 9.1 simulated design software. In future this work will be extended in tomodify TPG without affecting the MSIC vector and low-transition density. However the design through softwareverification only provides the sufficient results to users and this TPG named as “BIPARTITE-LFSR”.
关键词：BIST; Low Power; LFSR.