文章基本信息

标题：64 Bit Domino Logic Adder with 180nm CMOS Technology
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作者：M.B. Damle ; S. S. Limaye
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：4
页码：1-5
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Based on 180nm CMOS technology a 64 bit domino logic adder is designed for energy and speed optimization. The adder is designed using 4 bit slice of carry look-ahead adder. Multiple slices are connected in ripple carry fashion to obtain 64 bit adder. This result in considerable reduction in time as compared to nominal ripple carry adder. Implementation of equations of sum, generate and propagate are implemented in domino CMOS logic using TSMC 180nm library to provide energy optimization. The latency is no more than 33 clocks with a transistor count of 1504. Average power results are also presented in this paper with selected input vectors. average power for the design is calculated over the transient analysis. The simulation report from the TannerTool T-spice gives the following result after complete simulation, average power is 4.65 microwatt.
关键词：Domino logic; generator; ; propagator; 4-bit slice.