文章基本信息

标题：OPTIMIZED MULTIPLIER USING REVERSIBLE LOGIC GATES: A VEDIC MATHAMATICAL APPROACH
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作者：M.Anitha ; A.Rajani ; N.Pushpalatha 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：10
页码：3476-3482
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Multipliers are major components of any processor or computing machine. Digital signal processors(DSP) and performance of microcontrollers are evaluated on the basis of number of multiplications performed at unit time. Hence multiplier architectures are bound to increase the efficiency of the system. Vedic mathematics is one of the multiplier algorithms to perform multiplication operation. It is simple architecture with increased speed forms an unparalleled combination for serving any complex multiplication computations. with these additional highlights, implementing multiplier using reversible logic and further reduces power dissipation. Power dissipation is another important constraint in an VLSI design , which cannot be neglected. Here the type of multiplier is "Urdhva Tiryagbhyam(UT) multiplier". The operation of UT performs vertical and crosswise multiplication, implemented using reversible logic, which is simple procedure. This multiplier may find applications in Fast Fourier Transforms (FFTs), Embedded Systems and other applications of DSP like imaging, wireless communications. By using reversible logic implementation the speed and power dissipation is reduced. The quantum cost, garbage output, constant inputs and Total Reversible Logic Implementation Cost (TRLIC) are also reduced using reversible logic gates implementation.
关键词：Vedic Multiplier; Reversible Logic; ; Urdhva Tiryagbhyam; TRLIC