文章基本信息

标题：Design and implementation of IP Core Based Architecture of Telecommand System on chip (SoC) on FPGA
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作者：Anjan d ; Ashwini.s.shivannavar ; M. Z Kurian 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：5
页码：1992-1996
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The em erging developments in semiconductor technology have made possible to design entire system onto a single chip, comm only known as System -On-Chip (SoC). As the complexity of the rem otely located physical devices increases, the requirem ent for a greater telecomm anding capability and efficiency arises. This is achieved by em bedding pre-designed functions into a single SoC, which utilizes specialized reusable core (IP cores) architecture into complex chip. This papert is concerned with the design of telecommand and telemetry system for transfer of signals by the integration of Memory unit, telecommand and telemetry processor, EDAC unit (Error Detection And Correction). The results are analyzed using VIRTEX 4 FPGA devices. The IP core based architecture is implemented on FPGA device
关键词：EDAC unit; telecom mand; IP cores; Hamming code