文章基本信息

标题：Performance Analysis Of Double Edge triggered D flip flop
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作者：Namrata Rapartiwar ; Vinod Kapse ; Tarun kumar Sahu 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：5
页码：1900-1903
出版社：Shri Pannalal Research Institute of Technolgy
摘要：For low power VLSI circuits applications power consumption is a crucial. This paper proposed a new Double Edge Triggered D-Flip Flop (DETFF) which is suitable for low power applications. The proposed DETFF having minimum number of clocked transistors than existing designs. In that proposed design the transmission gates are replaced by NMOS to reduce the power. Simulation using SPICE and a 180 nm CMOS technology shows that this DETFF has ideal logic functionality, a simpler structure, lower lowest average power and least delay than existing designs. Further, the average power and the PDP are improved by 65.61% and 25.85% when compared with existing design respectively, which showing that proposed design is appropriate for low power and high performance applications.
关键词：DETFF; power; delay; PDP