文章基本信息

标题：DESIGN OF LDPC ARCHITECTURE USING VERILOG CODING
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作者：Manjunatha P N ; T.S Bharath kumar ; M Z Kurian 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：4
页码：1527-1531
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Low Density Parity Check codes are FEC codes and hence data rate is more. They are linear error correcting codes for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing close to the shannon's capacity[2]. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. In this Paper LDPC encoder and decoder architecture for coding 8-bit message vector will be analyzed and designed using verilog code.
关键词：Bit Flipping ; G-matrix; H-matrix; LDPC