文章基本信息

标题：Efficient Design of Arithmetic Logic Unit using Reversible Logic Gates
本地全文：下载
作者：Ravi Raj Singh ; Sapna Upadhyay ; Saranya S 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：4
页码：1474-1477
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Reversible logic is gaining wide importance as a logic design style for modern nanotechnology and quantum computing with minimal heat generation because the existing irreversible designs are reaching their physical limits. The reversible approach, therefore, results in improved computer architecture and arithmetic logic unit designs. An important block in the microprocessors is Arithmetic and Logic Unit (ALU). This paper proposes the design of ALU which have better performance in terms of quantum cost and transistor cost. The proposed ALU is realized using a carry save adder block which does not involve the propagation of carry bits. The proposed work leads to an improvement of 20% and 17% in terms of gate count and quantum cost respectively, as compared to earlier works in reversible ALU designs. The simulation and verification of the ALU is done using Cadence, Xilinx and Revkit tools.
关键词：ALU; Adder; Reversible Logic; Quantum ; Cost; Transistor Cost