文章基本信息

标题：Design and Implementation of Q-algorithm for Data Collision Reduction in EPC GEN-2 based on FPGA
本地全文：下载
作者：Rajeshwari T R ; Sandra Benzamin ; M. Z. Kurian 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：4
页码：1263-1266
出版社：Shri Pannalal Research Institute of Technolgy
摘要：EPC Gen-2 is an Electronic Product Code which is globally accepted standard in RFID. The data collision in RFID tags is reduced using anti-collision Q-algorithm. In this paper Design and implementation of Q-algorithm is described to solve data collision in RFID tags using Verilog HDL. The whole design will be developed using Xilinx ISE 12.2 and will be simulated using Modelsim 6.3c and will be implemented on Virtex 4 FPGA.
关键词：EPC Gen-2; RFID; Verilog HDL