文章基本信息

标题：COMPARISION OF PARALLEL BCD MULTIPLICATION IN LUT-6 FPGA AND 64-BIT FLOTING POINT ARITHMATIC USING VHDL
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作者：Vibha Mishra ; Vinod Kapse
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：3
页码：822-826
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Parallel BCD multiplication uses 6 look up tables using FPGAs. In this a combinational implementation maps quite well into the slice structure of the Xilinx virtex 5/virtex 6 families and it is highly pipelineable and in 64 bit floting point the scientific applications rely on floating point (FP) computation, often requiring the use of the 64 bit Floating Point format specified by the IEEE standard 754. The use of double precision (D.P.) data type improves the accuracy and dynamic range of the computation, but simultaneously it increases the complexity and performance of the arithmetical computation of the module. The design of high performance 64-Bit floating point units (FPUs) is thus of interest in this Document.