文章基本信息

标题：Area and Speed efficient Floating Point Unit design on Hybrid FPGA
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作者：Ankit Kumar Kusumakar ; Utsav Malviya
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：10
页码：2753-2755
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Implementation of area and speed efficient design of Floating Point Unit on Hybrid FPGA is gradually replacing the conventional slower FPUs which have lower speed while computing complex calculations includes Digital Signal Processing. Existing FPGA devices are not optimized for floating-point computations, and for this reason, floating-point operators consume a significant amount of FPGA resources. Implementation of area optimized FPU on a hybrid Field Programmable Gate Arrays (FPGAs) with new feature multiplication and addition. For multiplication Peasant Multiplication algorithm, also known Ancient Egyptian multiplication and proposed tree adder for addition purpose which is designed with VHDL, synthesized using Xilinx ISE 9.2i Webpack, simulated using ModelSim simulator and then implemented on Xilinx Virtex 2E FPGA.
关键词：Field Programmable Gate Arrays (FPGAs); ; Floating Point Unit (FPU); Integrated Software Environment ; (ISE); Digital Signal Processing (DSP); Configurable Logic ; Block (CLB); Look up Table (LUT).