文章基本信息

标题：Reconfiguration of Memory for High Speed Matrix Multiplication
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作者：Shamshad Shirgeri ; Pallavi Umesh Naik ; Rohini 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2013
卷号：2
期号：5
页码：1904-1908
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The paper entitled "RECONFIGURATION OF MEMORY FOR HIGH SPEED MATRIX MULTIPLICATION" is basically an enhancement in speed of matrix multiplication. The project aims at reducing the time involved in the operation. The system presented here makes use of three RAMS designated as MAT-RAM-A, MAT-RAM-B and MAT-RAM-C and system also consists of a control circuitry. This system works in two modes i.e., mode-1 and mode-2. In mode-1 the RAM's act as extensions of existing memory of the processor and in mode-2 the two RAMs MAT-RAM-A and MAT-RAM-B are configured as source for hardware with MAT-RAM-C working as destination for storage or resultant matrix after multiplication. The RAMs are configured back in mode-1, so that data can be read from MAT-RAM-C.
关键词：RAM; MAT-RAM-A; MAT- ; RAM-B and MAT-RAM-C; SIMD