文章基本信息

标题：Power Efficient Survivor Memory Architecture for Viterbi Decoder
本地全文：下载
作者：G.Sankar Babu ; Dr.M.Anto Bennet ; R.Kaushik Krishna 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：NCET
页码：217
出版社：S&S Publications
摘要：Vi terbi decoder i s a common module in communication system in which power anddecoding latency are constraint. Register exchange (RE) architecture has the lowest decoding latency L.However , i t is not sui table for communication system because of its high power consumption. In this paper,we propose a new SMU architecture which combines the concept of the trace-forward and trace-back. The decodinglatency of the proposed SMU algorithm is only L+M. Besides, we present a power efficient architecture for theproposed SMU algorithm.The power consumption of the proposed architecture is slightly higher than the 3-pointer even TB architecture.