文章基本信息

标题：Clock Tree Power Optimization of Three Dimensional VLSI System with Network
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作者：M.Saranya ; S.Mahalakshmi ; P.Saranya Devi 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2014
卷号：3
期号：4
页码：11758
出版社：S&S Publications
摘要：The proposed method is based on minimum-costmaximum-flow formulation to globally determine the treetopology, which maintains load balance and considers thewirelength between pulse generators and pulsed latches.Experimental results indicate that the proposed migrationapproach can improve the power consumption by 12% and13% with 7% and 70% skew improvements on averagecompared with the most recent paper on the industrialcircuits and ISPD-2010 benchmarks, respectively.Minimizing the size of a clock tree is known as an effectiveapproach to reduce power dissipation in modern circuitdesigns. However, most existing power-aware clock-treeminimization algorithms optimize power on the basis offlip-flops alone, which may result in limited power savings.To achieve a power and timing tradeoff, this paperinvestigates the pulsed-latch utilization in a clock tree forfurther power savings. This is the first paper to propose amigration approach to efficiently construct a clock treewith both pulsed-latches and flip-flops.
关键词：Clock tree migration; dynamic power reduction;pulse generator; pulsed latch.