文章基本信息

标题：Multi Valued Logic Based Design of Quaternary Adders in VHDL
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作者：Jasbir Kaur ; Parv Sapra
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：2
页码：1443
DOI：10.15680/IJIRSET.2016.0502037
出版社：S&S Publications
摘要：Small Silicon Area, Higher speed and low power consumption are the desired feature of any circuit, dueto the increasing need of portability in devices. Adders form an inevitable part of any system because they are the mostbasic units. Design of logic circuits using binary logic is limited by the number of interconnections. Multi Valued logicgives us an extension to the binary logic where any position can have more than two values. This paper reviews theneed of Multi valued logic and the implementation of the half and full adders using quaternary logic and simulated onXilinx ISE Design Studio 13.1
关键词：Multi Valued Logic; Quaternary Adders; VHDL; Xilinx