期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN:2347-6710
电子版ISSN:2319-8753
出版年度:2015
卷号:4
期号:12
页码:12351
DOI:10.15680/IJIRSET.2015.0412126
出版社:S&S Publications
摘要:The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP)integrated circuits design since the power consumption has become a critical issue. The low power design can utilize asmaller size and lighter-weight battery. A lot of research has been done on several LV and LP complementary metaloxide- semiconductor (CMOS) integrated circuit design techniques. Among many techniques used for the design of LVLP integrated circuits, the Bulk-driven (BD) principle offers a promising route towards this design for many aspectsmainly the simplicity. In this paper the advantages of the proposed 0.4V BD-CMOS inverter compared to theconventional Gate-Driven (GD) CMOS inverter with 180nm technology in Cadence Virtuoso is presented.