文章基本信息

标题：Design of Low Power High Speed Adders in McCMOS Technique
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作者：Shikha Sharma ; Rajesh Bathija ; RS. Meena 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
卷号：4
期号：7
页码：5196
DOI：10.15680/IJIRSET.2015.0407022
出版社：S&S Publications
摘要：Adder are the core component of processors and digital design architecture. Also, not only addition, butperforms many other arithmetic operations such as subtraction, division and multiplication. The focus of VLSItechnology is to reduce power consumption, enhancing the performance and speed of a digital circuit. Less powerconsumption is the ultimate attention for any computation. In this paper, 16 bit adders are designed using one suchtechnique i.e. McCMOS and compared for power dissipation, delay, leakage power and power delay product. Differenttypes of adders have been designed using Multiple channel CMOS (McCMOS) technology and compared withconventional with 45nm technology. The simulation result shows that the average power reduces to 30 – 35% less andPDP is reduced to 15- 17% than the power and PDP of the conventional CMOS. Hence the technique can be used forlow leakage high speed application. The simulation has been carried out in tanner tool EDA 14.1 with 1V powersupply.
关键词：Carry Save Adder; Carry Select Adder; McCMOS; ALU (Arithmetic logic Unit).