The demand for ever smaller, portable, energy-efficient and high-performance electronic systems has been the primary driver for CMOS technology scaling. As CMOS scaling approaches physical limits, it has been fraught with challenges that required introduction of newer materials, manufacturing processes and device structures. High- oxide and metal-gate stack was introduced to mitigate oxide leakage which became a significant concern for sub-65nm CMOS technologies. Thin body, undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage as battery life for mobile devices rose to prominence. 3D transistors such as double-gate FinFET and trigate transistors have been introduced to improve ON current and reduce subthreshold leakage without compromising layout efficiency that is crucial for device density which leads to lower costs. These innovations have allowed sustained scaling of CMOS technology which will continue to dominate semiconductor manufacturing for reasons that are both technological and financial. In CMOS technology, charge conveys logic information. Movement of charge is central to computation and storage, which entails a minimum energy dissipation of the order k_B T per switching event. It has been argued that energy dissipation defines the fundamental limit of CMOS scaling.