文章基本信息

标题：A Self -Test Approach Based Arithmetic BIST for Test Pattern Generation
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作者：Shaik anjumara ; P. Bala Murali Krishna
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310158
出版社：S&S Publications
摘要：The objective of the BIST is to reduce power dissipation without affecting the fault coverage. Weightedpseudorandom built-in self - test (BIST) schemes have been utilized in order to drive down the number of vectors toachieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5have been successfully utilized so far for test pattern generation, since they result in both low testing time and lowconsumed power. In this approach, the single input change patterns generated by a counter and a gray code generatorare Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. Sinceaccumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down thehardware of BIST pattern generation, as well. From the implementation results, it is verified that the testing power forthe proposed method is reduced by a significant percentage.
关键词：Built-in self-test(BIST); VLSI testing; weighted test pattern generation; low power linear feedback shift;register [LP-LFSR]