文章基本信息

标题：Comparative Analysis and FPGA Implementation of Vedic Multiplier for various Bit Lengths using Different Adders
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作者：Parul Agrawal ; Rahul Sinha
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：10
DOI：10.15680/IJIRCCE.2015.0310153
出版社：S&S Publications
摘要：This paper describes the design of Vedic Multiplier based on Urdhva Trigbhyam technique ofmultiplication. It is one of the ancient Vedic sutras for multiplication it means vertical & crosswise. The papercompares the design of Vedic Multiplier for different bit lengths based on Ripple Carry Adder & Kogge Stone Adder.For the highly efficient processor, multiplier plays an important role. It has been found that Kogge Stone Adder isfastest Parallel Prefix Adder, hence the delay in Vedic Multiplier based on Kogge Stone Adder is less as compared tothat based on Ripple Carry Adder.The delay for 16bit Vedic Multiplier using Ripple Carry Adder has been found to be29.051ns whereas using Kogge Stone Adder has been found as 27.499ns. The design has also been compared basedon levels of logic, memory utilization. The proposed algorithm has been designed using Verilog HDL. Implementationhas been done using Xilinx 14.4 with family Spartan6, device as xc6slx45, package csg324 with speed grade of -3.
关键词：KSA; RCA; Urdhva Trigbhyam; Vedic Multiplier