文章基本信息

标题：Simulation and Synthesis of a Novel Approach for Parallel BCD Multiplier
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作者：P.Shalini ; J. Prasad Babu
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：7
DOI：10.15680/ijircce.2015. 0307072
出版社：S&S Publications
摘要：Nowadays, to perform to perform arithmetic operations in financial, commercial, internet and scientificbased applications, decimal multiplication plays a crucial role. In this paper, a fully pipelined decimal multiplier hasbeen designed consists of carry save adder and the same grouped to BCD-4221. The proposed design is presented basedon multiplier operands recoded in Signed Digit (SD) Radix-10, it also consists of a simplified partial products generatorand decimal adders. Different types of models has been proposed in several ways but these synthesis and simulationresults were exhibits the optimized performance parameter values in terms of delay/speed and area
关键词：Arithmetic Operations; BCD; Decimal Floating Point; Signed Digit Radix-10; FPGA.