文章基本信息

标题：Calculation of Power Consumption in 10 T CMOS SRAM Cell with 0.6 µm Technology Using Microwind 2 Tool
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作者：Vertika Sarkari ; Aditya Vikram Singh ; Ajita Pathak 等
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：6
DOI：10.15680/ijircce.2015.0306006
出版社：S&S Publications
摘要：Due to the advancement of low power CMOS technology, the fast and low power static random accessmemory has become an important component of many VLSI chips. This paper is focused on reduction in powerconsumption during write operation. We have assumed that the proposed SRAM is designed by using Microwind 2 ICdesign tool with CMOS 0.6μm technology. The proposed SRAM cell is designed with the dual word line approach thatis circuit used two separated word line for write (WWL) and read (RWL) operation. In proposed 10 T SRAM with 0.6μm CMOS technology the average write power consumption is being reduced by using two tail transistor at bottom ofpull down network of inverters and the bit line and bit bar line are cross coupled with theses transistor for propercharging and discharging of bit line during write operation. The result is compared with conventional 6T SRAM cellthat is also designed with 0.6 μm CMOS technology; there is a decrease in average write power consumption inproposed SRAM by 38.6 %.
关键词：CMOS 6T SRAM; Dynamic power; Threshold Voltage; width to length ratio.