文章基本信息

标题：Low Power Phase Locked Loop Design with Minimum Jitter
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作者：Krishna B. Makwana ; Prof. Naresh Patel
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：5
DOI：10.15680/ijircce.2015.0305042
出版社：S&S Publications
摘要：This paper describes a design of phase locked loop system with low power and minimum jitter. PLLswith high speed, low noise and wide bandwidth with fast acquistion time are preferred. A PFD with low dead zone,charge pump with passive low pass filter and a low noise, wide tuning VCO are integrated in the PLL system. ATelescopic OTA based VCO with wide tuning range of 450MHz to 1.9GHz and power consumption of 0.30mW isdesigned.. The PFD modeled is using 15 transistor and conventional charge pump with second order loop filter is used.Integrating this VCO in a PLL system offers low jitter and wide bandwidth. The results prove that maximum pull-intime is 150ns and the power consumed by this PLL system is 606uW at 1.5GHz.Measured jitter is 30ps in this PLL.
关键词：Phase Locked Loop (PLL); Phase Frequency Detector (PFD); Charge Pump (CP); Loop Filter; Voltage;Controlled Oscillator (VCO); Lock-in range; Lock time; Jitter