期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN:2320-9798
电子版ISSN:2320-9801
出版年度:2015
卷号:3
期号:5
DOI:10.15680/ijircce.2015.0305014
出版社:S&S Publications
摘要:Reversible logic concept gaining much attention of researchers due to its characteristics of generatingloss-less system. Reversible logic technology do not erase information hence no heat dissipation. In this paper a newreversible SMT logic gate has been proposed .The proposed three inputs, three outputs reversible logic based SMT gatehas designed for Logical, Boolean and Arithmetical functions. This gate needs only one clock cycle to performmultifunctional operation and produce no garbage output. In the present investigation reversible half adder and halfsubtractor gate has been successfully realized by SMT gate. It produces zero garbage outputs. The proper codingproves that the proposed gates are fulfilling the requirement of reversible logic gate. In present paper differentproperties of SMT gate has been simulated using VHDL.
关键词:Reversible logic; Reversible gate; Power dissipation; SMT gate; Half-adder and half subtractor