文章基本信息

标题：Vedic Multiplier in VLSI for High Speed Applications
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作者：G.Ramachandran ; T.Muthumanickam ; P.M.Murali 等
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：3
DOI：10.15680/ijircce.2015.0303136
出版社：S&S Publications
摘要：Today most of the processor requires very high speed of operation. Usually DSP processors are based onmathematical approaches. In that multiply-accumulate operation plays vital role. Compared to addition, multiplicationprocess takes large amount of time thus reduces the speed of the processor, consumes some amount of power and area.In this paper we proposed two techniques to improve processor speed based on Vedic mathematics. In Vedicmathematics among 16 sutras, 2 sutras are applicable for multiplication. First method URDHAVA TRIYAKBHYAMsutra which is similar to array multiplication .When number of bits increases, gate delay and area increases slowlycompared to other multiplier. So the advanced technique called NIKHILAM sutra is employed. These sutras are meantfor faster mental calculation. Though faster when implemented in hardware, it consumes more power than theconventional ones. In this project both the techniques are compared and found that nikhilam is best. This projectpresents a technique to modify the architecture of the Vedic multiplier by using some existing methods in orderincrease the processor speed.
关键词：Array multiplier; DSP;VLSI