期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN:2320-9798
电子版ISSN:2320-9801
出版年度:2015
卷号:3
期号:3
DOI:10.15680/ijircce.2015.0303046
出版社:S&S Publications
摘要:Memory are inherent part of the nearly all of the digital models and so minimization of power usage of amemory is major role in upgrading the system efficiency, performance reliability. In the paper new multi-threshold onebit-line SRAM cell is proposed , for both read and write operation one bit-line is used. Minimization of power usagebecause of one bit-line usage and more read stability than conventional multi threshold SRAM cell. In between theproposed multi-threshold one bit-line SRAM cell and conventional multi-threshold SRAM cell comparison will be heldin terms of power usage, SNM, delay. The proposed multi-threshold one bit-line SRAM cell usage 94.6% reduction inpower in write 1 operation, 93.1% reduction in power in read 1 operation than multi-threshold SRAM.We drawn the schematics using virtuoso ADE of cadence ,and all simulation data are taken out using cadencespectre analyzer with 45nm technology library at 1.8v.
关键词:One bit-line; Multi-threshold SRAM cell; less power ;Read stability ; SRAM(static random access;memory); SNM(static noise margin)