文章基本信息

标题：FPGA Implementation of 3/6 SRFFT Algorithm for Length 6*m DFTS
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作者：M. Sathya ; M.B.Annadurai
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：11
出版社：S&S Publications
摘要：The Fast Fourier Transform (FFT) requires high Computational power, ability to choose the algorithmand architecture to implement it. This project explains the realization of a 3/6 FFT processor based on a pipelinearchitecture. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaininghigh performance at economical price and a short time of realization. FPGA can be used with segmented arithmetic ofany level of pipeline in order to speed up the operating frequency. The processor has been simulated up to 200 MHz,with an Xilinx Spartan 3E as a target device, for a transform length of 6 complex points. To combine the higherparallelism of the 6-FFTs and the possibility of processing sequences having length of any power of 6.Thesimultaneous operation of multipliers and adder-subtracters implicit in the 3/6 FFT, leads to faster operation at the samedegree of pipeline. The 3/6 FFT algorithm is implemented in Xilinx FPGA Spartan 3E.
关键词：Fast Fourier transform (FFT); Field Programmable Gate Array (FPGA); 3/6 FFT