文章基本信息

标题：Design and Verification of High Speed SDRAM Controller with Adaptive Bank Management and Command Pipeline
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作者：Ganesh Mottee ; P.Shalini
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：6
出版社：S&S Publications
摘要：As the performance gap between microprocessors and memory continues to increase,main memoryaccesses result in long latencies which become a factor limiting system performance. Previous studies show that mainmemory access streams contain significant Localities and SDRAM devices provide parallelism through multiple banksand channels.These locality and parallelism have not been exploited thoroughly by conventional memory controllers. Inthis thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied tomemory controller design with the goal of reducing observed main memory access latency. The application of thesynchronous dynamic random access memory (SDRAM) has gone beyond the scope of personal computers for quite along time. It comes into hand whenever a big amount of low price and still high speed memory is needed. Most of thenewly developed stand alone embedded devices in the field of image, video and sound processing take more and moreuse of it. The big amount of low price memory has its trade off – the speed. In order to take use of the full potential ofthe memory, an efficient controller is needed. Efficient stands for maximum random accesses to the memory both forreading and writing and less area after implementation.