文章基本信息

标题：A Feasible Approach to Design a Cmos Domino Circuit at Low Power VLSI Application Design
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作者：Pallavi Sharma ; Dr Subodh Wariya
期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：7
页码：13055-13060
出版社：IJECS
摘要：Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement ascompared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and chargesharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOSinverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit.In this paper we have proposed a novel circuit for domino logic which has less area and has less power-delay product (PDP) as compared toprevious reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is notconducting. Then comparison analysis has been carried out by simulating the circuits in 90nm CMOS process technology from TSMC usingTanner EDA 14.11.
关键词：Dynamic logic; Dynamic Node; High speed; Diode Footed Domino; Noise Tolerance; Propagation delay; Power Consumption;Robustness; Domino CMOS logic