文章基本信息

标题：A 16-Bit Ripple Carry Adder Design Using High Speed Modified Feedthrough Logic
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作者：Avinash Singh ; Dr. Subodh Wairya
期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：5
页码：12058-12061
出版社：IJECS
摘要：This paper presents the design and simulation of high speed 16-bit ripple carry adder using a new CMOS logic family calledfeedthrough logic(FTL). FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOStechnologies. The proposed circuit has very small propagation time delay as compared to existing dynamic logic circuits. The proposedmodified feedthrough logic completely eliminates the output distortion occurs in existing FTL structure having reference voltage Vdd/2. InThis paper, a long chain of inverters (20-stages) and 16-bit ripple carry adder is designed by modified feedthrough logic. Then comparisonanalysis has been carried out by simulating the circuits in 180nm CMOS process technology from TSMC using Tanner EDA 14.11.
关键词：Feedthrough logic(FTL); High speed; Ripple carry adder(RCA); Propagation delay; Domino CMOS logic.