文章基本信息

标题：Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode Domino Logic
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作者：Monika Jain ; Dr. Subodh Wairya
期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2014
卷号：3
期号：10
页码：8748-8751
出版社：IJECS
摘要：Power saving is more important than any other thing now a days because high speed and low power design continues to getmore attention. In this paper, low power dynamic circuit [1] has been implemented at 180nm, 90nm, 45nm and 32nm technology, usingHSPICE. The simulations are performed on CosmosScope. The power saved is up to 46%, 50%, 51% and 73% for 180nm, 90nm, 45nmand 32nm technology respectively using the proposed footed diode circuit [1]. Domino buffer and a two input AND gate have been usedas a test circuit to show the simulation results
关键词：Domino logic; power consumption; PDB based domino logic; footed diode