文章基本信息

标题：Efficient Architecture for the Convolution Encoder and Viterbi Decoder for FPGA Implementation
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作者：Soni, V. ; Nemade, S
期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2014
卷号：5
期号：2
页码：293-296
出版社：IJECCE
摘要：Error correcting codes (ECC) are one of the fundamental building blocks of an efficient communication system and utilization of proper encoding technique guarantees the error free communication in noisy environment although there are many types of ECC available the convolution codes are specifically preferred where the large constrain length are required with lower encoder complexity (like deep space communication). In this paper we are presenting an efficient design structure for the convolution encoder and decoder (Viterbi) for the FPGA implementation we also analyzed the developed mode for noisy situations for it correcting capabilities. The proposed model is synthesized and simulated using Xilinx ISE 14.4 software which shows that the proposed design effectively reduces the resource requirements and the power analysis on X-Power Analyzer shows considerable reduction in power requirements.
关键词：Error Correction Codes ECC; Forward Error Correcting Codes FEC; Convolution Encoder; Viterbi Decoder; VHDL